Scan chain is a technique used in Design For Test. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC. A special signal called scan enable is added to a design. When this signal is asserted, every flip-flop in the design is connected into one or more long shift registers, one input pin provides the data to each chain, and one output pin is connected to the output of each chain. Then using the chip's clock signal, an arbitrary pattern can be entered into each chain of flip flops, and/or the state of every flip flop can be read out. Test patterns are shifted in via the scan chain(s), functional clock signals are pulsed to test the circuit during the “launch/capture cycle(s)”, and the results observed are then shifted out to chip output pins and compared against the expected “good machine” results.
In scan chain testing, optimization, i.e., maximizing shift frequency, thus minimizing test times, is desired. The scan chain shift frequency is limited by:                a) The inherent timing of the scan chain, determined by the set-up and hold times of the scan flip flops, and        b) The input path to the first flip flop and output path from the last flip flop. The frequency response of these paths is dependent on such factors as Vdd, temperature, power grid, and process details; and        c) I/O timing.        
The ATE input/output timing in current technology generally is a significant limitation on the scan test speeds. Increasing the scan speed beyond a safe timing margin can cause instability in scan test results. Therefore, the usual practice is to reduce the test speed so as to build in large timing margins, giving stable results, but increasing the test time.